Programmable logic devices such as PLAs, PALs, ASICs, FPGAs and EPLDs are well known in the field. Such devices are described in such prior publications as Birkner, U.S. Pat. Nos. 4,124,899; Freeman, 4,870,302; Carter, 4,706,216; Elgamal et al., 4,758,745; and Kaplinsky, 4,847,612. All these patents are incorporated herein by reference. These devices all have hardware which can be programmably connected together to perform a logic function selected by a user. Once these devices have been programmed by the user, certain external pins serve as input pins, others pins serve as output pins and in some cases some serve as input/output pins. The device provides signals on the output pins in response to signals and combinations of signals placed on input pins as determined by the function which has been programmed into the device by the user.
Users employ these programmable devices to solve a wide variety of problems, and manufacturers have responded by offering a wide variety of device sizes and speeds as well as device designs. Some devices are optimized for speed, some for flexibility, some for complexity, and some for low cost. Typically higher speed, higher flexibility, and larger size are each associated with higher cost. With existing devices, high speed is typically provided and must be paid for whether the user needs it or not. Some users want a large number of signal pins but can tolerate low speed output buffers. No device with these characteristics has been available.